Electrical computers and digital processing systems: memory – Address formation – Address mapping
Patent
1997-03-31
2000-07-11
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Address formation
Address mapping
711204, G06F 1210
Patent
active
06088780&
ABSTRACT:
A method and apparatus for implementing a page table walker that uses at least one of a default page size and a page size selected for a virtual address space to position a sliding field in a virtual address. According to one aspect of the invention, an apparatus for use in a computer system is provided that includes a page size storage area and a page table walker. The page size storage area is used to store a number of page sizes each selected for translating a different set of virtual addresses. The page table walker includes a selection unit coupled to the page size storage area, as well as a page entry address generator coupled to the selection unit. For each of the virtual address received, the selection unit positions a field in that virtual address based on the page size selected for translating the set of virtual addresses to which that virtual address belongs. In response to receiving the bits in the field identified for each of the virtual addresses, the page entry address generator identifies an entry in a page table based on those bits.
REFERENCES:
patent: 4356549 (1982-10-01), Chueh
patent: 4980816 (1990-12-01), Fukuzawa et al.
patent: 5058003 (1991-10-01), White et al.
patent: 5375214 (1994-12-01), Mirza et al.
patent: 5412787 (1995-05-01), Forsyth et al.
patent: 5446854 (1995-08-01), Khalidi et al.
patent: 5475827 (1995-12-01), Lee et al.
patent: 5479627 (1995-12-01), Khalidi et al.
patent: 5526504 (1996-06-01), Hsu et al.
patent: 5555387 (1996-09-01), Branstad et al.
patent: 5617554 (1997-04-01), Alpert et al.
patent: 5752275 (1998-05-01), Hammond
PCT International Search Report (PCT/US98/02047), 9 pages, dated Aug. 14, 98, authorized officer: Kevin Verbrugge.
i750, i860 & i960, Processors and Related Products, Intel Corporation (1993) 7 Pages.
Shanley, et al., "ISA System Architecture, New Revised Edition", vol. 1, pp. 137-156 (1991 & 1993).
Kane, et al., "MIPS RISC Architecture", Prentice Hall, Englewood Cliffs, New Jersey, Ch 6, 57 Pages, Ch 4, 30 Pages (1992).
POWERPC 601, RISC Microprocessor User's Manual, Memory Management Unit, Ch 6, Motorola, 63 pages, (1993).
Bryg William R.
Burger Stephen
Hammond Gary N.
Hays Jim
Ross Jonathan Kent
Chan Eddie P.
Institute for the Development of Emerging Architecture L.L.C.
Verbrugge Kevin
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