Method and apparatus for a test control circuit of a semiconduct

Details Method and apparatus for a test control circuit of a semiconduct Method and apparatus for a test control circuit of a semiconduct

1995-12-12

1997-04-01

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Testing

3652257, G11C 700

Patent

active

056173660

ABSTRACT:
A test control circuit and method for performing a standardized test in a semiconductor memory device which has a structure such that it is difficult to perform a test operation using a standardized test mode. The test control method of a semiconductor memory device includes the steps of: arranging in the memory device a fuse capable of being electrically blown; receiving a plurality of external input signals applied to the memory device; generating a blocking signal based on the plurality of external input signals and the status of the electrical fuse; generating a parallel test enable signal based on the blocking signal and the plurality of external input signals, wherein, when the blocking signal is of a first logic level, the parallel test enable signal will indicate performance under either a parallel test mode or a normal operation mode based on the plurality of external input signals, and when the blocking signal is of a second logic level, the fuse is blown and the parallel test enable signal permanently indicates operation in a normal opreration mode.

REFERENCES:
patent: 5140554 (1992-08-01), Schreck et al.
patent: 5228000 (1993-07-01), Yamagata
patent: 5270983 (1993-12-01), Wuertz et al.
"A 90ns 1Mb DRAM with Multi-Bit Test Mode", by Masaki Kumanoya, Kazuyasu Fujishima, Katsuhiro Tsukamoto, Yasumasa Nishimura, Kazunori Saito, Takayuki Matsukawa, Tsutomu Yoshihara, Takao Nakano 1985 IEEE International Solid-State Circuits Conference, pp. 240-241.

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