Semiconductor device having reduced-width polysilicon gate and n

Details Semiconductor device having reduced-width polysilicon gate and n Semiconductor device having reduced-width polysilicon gate and n

1997-12-17

2000-07-11

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438585, 438770, H01L 21336

Patent

active

060872381

ABSTRACT:
A semiconductor device having a reduced polysilicon gate electrode width is provided along with a process for manufacturing such a device. In accordance with the present invention, a semiconductor device may be formed by forming an oxidation-resistant barrier layer over a substrate. At least one polysilicon block is formed over the barrier layer. A dopant is implanted through the barrier layer into the substrate. The polysilicon block is oxidized to grow an oxide layer on exposed surfaces and thereby reduce the width of the block. The oxide layer then can be removed to form a gate electrode having a reduced width. Plural implantations and oxidation-removal can be carried out as desired.

REFERENCES:
patent: 4869781 (1989-09-01), Euen et al.
patent: 5476802 (1995-12-01), Yamazaki et al.
patent: 5650649 (1997-07-01), Tsukiji
patent: 5858843 (1999-01-01), Doyle et al.
U.S. application serial No. 08/924,455, filed Aug. 29, 1997.

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