Test structures for monitoring gate oxide defect densities and t

Details Test structures for monitoring gate oxide defect densities and t Test structures for monitoring gate oxide defect densities and t

1997-03-07

2000-02-22

Loke, Steven H.

Active solid-state devices (e.g., transistors, solid-state diode

Test or calibration structure

257296, H01L 2358, H01L 27108

Patent

active

060283246

ABSTRACT:
An ensemble of test structures comprising arrays of polysilicon plate MOS capacitors for the measurement of electrical quality of the MOSFET gate insulation is described. The test structures also measure plasma damage to these gate insulators incurred during metal etching and plasma ashing of photoresist. The structures are formed, either on test wafers or in designated areas of wafers containing integrated circuit chips. One of the test structures is designed primarily to minimize plasma damage so that oxide quality, and defect densities may be measured unhampered by interface traps created by plasma exposure. Other structures provide different antenna-to-oxide area ratios, useful for assessing plasma induced oxide damage and breakdown. The current-voltage characteristics of the MOS capacitors are measured by probing the structures on the wafer, thereby providing timely process monitoring capability.

REFERENCES:
patent: 5350710 (1994-09-01), Hong et al.
patent: 5393701 (1995-02-01), Ko et al.
patent: 5434108 (1995-07-01), Ko et al.
Shin et al, "Thickness and other Effects on Oxide and Interface Damage by Plasma Processing", IEEE International Reliability Physics Proceedings, 1993, pp. 272-279.

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