Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-07-03
2000-02-22
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438253, 438238, 438239, 438255, 438381, 438397, H01L 218242, H01L 218234, H01L 218244, H01L 2120
Patent
active
060279672
ABSTRACT:
A method of making a capacitor comprising providing a space extending between a pair of gate stacks on a semiconductor substrate, the space exposing a charge conducting region on the semiconductor substrate. A BPSG layer is formed over the pair of gate stacks. A hard mask layer comprising alternating layers of doped polysilicon and undoped polysilicon is formed over the BPSG layer during a single deposition cycle of depositing polysilicon. Portions of the hard mask layer and the BPSG layer are selectively removed to form topographical structures extending above the gate stacks and having a trench therebetween. A spacer etch and a contact etch are performed to expose the charge conducting region. A doped polysilicon spacer is formed on the lateral side of each topographical structure. A second group of alternating layers of doped polysilicon and undoped polysilicon is formed over the topographical structures and within the trench. Portions of the hard mask layer and the second group of the alternating layers of doped polysilicon and undoped polysilicon are selectively removed. An etch selective to the doped polysilicon is performed to selectively remove the undoped polysilicon to create a structure with spaced apart doped polysilicon layers. A dielectric layer and an electrically conductive cell plate are formed over the alternating layers of the doped polysilicon and the undoped polysilicon. The semiconductor substrate is heated to diffuse dopant in the doped polysilicon into the undoped polysilicon. The resultant novel capacitor has a fin-like structure extending therefrom which increase the surface area thereof.
REFERENCES:
patent: 4093503 (1978-06-01), Harris et al.
patent: 4571817 (1986-02-01), Birritella et al.
patent: 5153813 (1992-10-01), Oehrlein et al.
patent: 5160987 (1992-11-01), Pricer et al.
patent: 5358908 (1994-10-01), Reinberg et al.
patent: 5484740 (1996-01-01), Cho
patent: 5532182 (1996-07-01), Woo
patent: 5637523 (1997-06-01), Fazan et al.
patent: 5721152 (1998-02-01), Jenq et al.
patent: 5753948 (1998-05-01), Nguyen et al.
patent: 5817553 (1998-10-01), Stengl et al.
patent: 5851876 (1998-12-01), Jenq
patent: 5869367 (1999-02-01), Fazan et al.
Schnakenberg et al., TMAHW Etchants for Silicon Micromachining, 91CH2817-5/91/000-0815,IEEE,815-818, 1991.
G.L. Kuhn et al., Thin Silicon Film on Insulating Substrate, J. Electrochem. Soc. Solid State Science and Technology, vol. 120, No. 11, 1563-1566, 1973.
Super Q Etch, Olin Electronic Materials, Olin Corporation, Chandler, AZ (1993).
Box Cell, Toshiba.
Li Li
Parekh Kunal R.
Wu Zhiqiang
Berezwy Neal
Micro)n Technology, Inc.
Niebling John F.
LandOfFree
Method of making a fin-like stacked capacitor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of making a fin-like stacked capacitor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of making a fin-like stacked capacitor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-519981