Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation
Patent
1997-04-25
1999-12-21
Whitehead, Jr., Carl
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
Insulated gate formation
438590, 438652, 438655, H01L 213205
Patent
active
060048697
ABSTRACT:
A method for forming conductive lines such as interconnects and DRAM gate stacks. A blanket stack is formed on a substrate including a conductive diffusion barrier, a near noble metal such as cobalt, followed by a silicon layer and a top insulator layer. The blanket stack is patterned with resist to define the conductive lines. The stack is dry etched down to the near noble metal layer. The resist is then removed and the stack is annealed to react the near noble metal and silicon to form a conductive compound having fine grain size. The unreacted noble metal is then wet etched, using the conductive diffusion barrier as a wet etch stop. A further dry etch is then performed down to the substrate, using the top insulator layer as a mask. In this manner, only one mask is required to form the conductive line.
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Duong Khanh
Jr. Carl Whitehead
Micro)n Technology, Inc.
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