Static memory using a MIS field effect transistor

Details Static memory using a MIS field effect transistor Static memory using a MIS field effect transistor

1987-09-24

1989-03-21

Moffitt, James W.

Static information storage and retrieval

Read/write circuit

Precharge

365154, 365208, G11C 700

Patent

active

048150401

ABSTRACT:
In a selected column, a pull-up transistor pair is not selected but, instead, a transmission gate transistor pair is selected. In the read mode, the transmission gate transistor pair serves as pull-up loads between the bit line pair. However, the transmission gate transistor pair is kept off until the voltage across the bit line pair is decreased from the power supply potential level to the threshold voltage level of the transmission gate transistors. Therefore, no DC current path is formed in the bit line pair when the voltage across the bit line pair is within a range from a voltage equal to the power supply potential level to a potential lower than the power supply potential by an amount equal to the threshold voltage level, and the rate of increase of a potential difference across the bit line pair is determined by a pull-in current of the memory cell. Therefore, a high-speed sense operation can be realized. In the write mode, the transmission gate transistor pair serves a bit line pull-up function. Since no normally-ON bit line load transistor is arranged, no direct current path including the bit line pair is present, and hence, low power consumption can be achieved.

REFERENCES:
patent: 4370737 (1983-01-01), Chan
patent: 4539494 (1985-09-01), Kurafuji
patent: 4658382 (1987-04-01), Tran et al.
Minato et al., "A 20ns 64K CMOS SRAM," IEEE International Solid-State Circuits Conference, ISSCC Digest of Technical Papers, pp. 222-223, Feb. 23, 1984.

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