Semiconductor memory having multiple level storage structure

Details Semiconductor memory having multiple level storage structure Semiconductor memory having multiple level storage structure

1984-12-24

1987-04-28

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365149, 365230, G11C 1140

Patent

active

046619291

ABSTRACT:
In a semiconductor memory includes a memory array consisting of a plurality of memory cells respectively having at least one storage capacitor, an addressing circuit which designates location of each memory cell, data lines which transmit data connected to said memory cells and data writing and reading circuits connected to said data lines. The semiconductor memory has a multiple level storage structure. In particular, the memory includes an arrangement for sequentially applying, on a time series basis, different voltages of at least 3 levels or more to the gate of a switching MOS transistor of said memory cells, a bias charge supplying means as said data reading circuit and a column register providing at least two or more storage cells which temporarily store said data.

REFERENCES:
patent: 4567579 (1986-01-01), Patel et al.

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