Local interconnect for integrated circuits

Details Local interconnect for integrated circuits Local interconnect for integrated circuits

1990-08-14

1991-12-24

Hille, Rolf

357 67, 357 68, H01L 2348, H01L 2946, H01L 2954, H01L 2962

Patent

active

050757610

ABSTRACT:
A silicide layer, to improve conductivity, is formed over a first layer of polycrystalline silicon, followed by a second layer of polycrystalline silicon. This structure is then patterned to form gate regions over active areas. A layer of metal silicide is formed over the entire surface of the chip, and patterned to form local interconnect. Etching of the second metal silicide layer is stopped by the second polycrystalline silicon layer, thereby protecting the first metal silicide layer from damage.

REFERENCES:
patent: 4640004 (1987-02-01), Thomas et al.
patent: 4658496 (1987-04-01), Beinvogl et al.
patent: 4673968 (1987-06-01), Hieber et al.
patent: 4717686 (1988-01-01), Jacobs et al.
patent: 4724223 (1988-02-01), Ditchek
patent: 4740479 (1988-04-01), Neppl et al.
patent: 4804636 (1989-02-01), Groover, III et al.
patent: 4829363 (1989-05-01), Thomas et al.
patent: 4889823 (1989-12-01), Bertagnolli et al.

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