Method of fabricating double poly-gate high density multi-state

Details Method of fabricating double poly-gate high density multi-state Method of fabricating double poly-gate high density multi-state

1998-06-19

2000-10-17

Fourson, George

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438278, H01L 21336

Patent

active

061331023

ABSTRACT:
A method to fabricate double poly gate high-density multi-state flat mask ROM cells on a silcon substrate is disclosed. The method comprises the following steps. Firstly, an in-situ n+ first polysilicon/pad oxide layer is deposited on the silicon substrate, and then an ARC layer such as nitride layer is deposited to improve the resolution during the lithography process for pateterning a first formed word line. After forming a plurality of dual nitride spacers on sidewalls of the first patterned gate, a first photoresist coating on all resultant surfaces except the two predetermined regins, a first boron or BF.sub.2.sup.+ coding implant into the silicon substrate is carried out. The photoresist is then stripped and an oxidaiton process conducted in O.sub.2 ambient to grow oxide layers on all surfaces of the silicon substrate using the nitride layer as a hard mask. Subsequently, a second silicon layer (polysilicon or amorphous silicon) is deposited to refill all of the spaces between the two nearest first formed gates, and then a thick oxide layer is formed on the second polysilicon layer. After that, a CMP process is done to form a flat surface using the nitride as an etching stopper. Finally, a second photoresist mask is formed on all surfaces except a second predetermined region. Then a high energy, second boron coding implant is implanted into said predetermined regions to form the multi-state mask ROM.

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Bertagnolli et al., ROS: An Extremely High Density Mask ROM Technology Based On Vertical Transistor Cells, 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 58 and 59.

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