Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-07-02
2000-10-17
Dang, Trung
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438253, 438254, 438258, 438238, H01L 218242
Patent
active
06133085&
ABSTRACT:
A method of forming a bottom storage node of a DRAM capacitor over a contact plug is disclosed. The method comprises the steps of: depositing an oxide layer over the contact plug; etching the oxide layer using a first photoresist layer having with a first masking pattern, the first masking pattern allowing the removal of the oxide layer over the contact plug; depositing a polysilicon layer over the oxide layer and in electrical contact with the contact plug; forming a second photoresist layer having a second masking pattern onto the polysilicon layer, the second masking pattern being substantially similar to the first masking pattern, but rotated by a predetermined angle; and etching the polysilicon layer in accordance with the second photoresist layer until the oxide layer is reached.
REFERENCES:
patent: 5821142 (1998-10-01), Sung et al.
patent: 6020234 (2000-02-01), Li et al.
patent: 6037234 (2000-03-01), Hong et al.
Dang Trung
Taiwan Semiconductor Manufacturing Corporation
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