Nonvolatile semiconductor memory device

Details Nonvolatile semiconductor memory device Nonvolatile semiconductor memory device

1980-08-25

1984-01-10

Hecker, Stuart N.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365185, G11C 700

Patent

active

044256329

ABSTRACT:
There is provided a nonvolatile semiconductor memory device which comprises memory cells arranged in the form of a matrix and formed of MOS FET's each having a floating gate, a plurality of word lines each coupled to memory cells on the same row, and a plurality of data lines each coupled to memory cells on the same column. In this semiconductor memory device, the sources of the MOS FET's forming the memory cells are coupled to a resistor.

REFERENCES:
patent: 3836894 (1974-09-01), Cricchi
patent: 4301518 (1981-11-01), Klass
IEEE Transactions on Electron Devices, vol. ED-24, No. 5, May 1977, pp. 606-610, New York (USA); B. Rossler: "Electrically Erasable and Reprogrammable Read-Only Memory Using the n-Channel SIMOS One-Transistor Cell", p. 606, col. 2, line 11; p. 607, col. 1, line 7; p. 608, col. 1, lines 35-38, p. 608, col. 2, line 12-16.
Patents Abstracts of Japan, vol. 2, No. 65, 5/18/78, p. 2307 E 78; Japanese Kaoki No. 53682 issued to Ishikawa (Toshiba) & JP-A-53 32 682 (Toshiba) (3/28/78).
IEEE International Electron Devices Meeting, Washington, Dec. 4-6, 1978, pp. 478-482, New York (USA): E. Sun et al.: "Breakdown Mechanism in Short-Channel MOS Transistors", p. 3, lines 28-40.

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