Semiconductor memory with column decoded bit line equilibrate

Details Semiconductor memory with column decoded bit line equilibrate Semiconductor memory with column decoded bit line equilibrate

1990-12-13

1994-03-22

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Precharge

36518901, 3652335, G11C 700, G11C 1134

Patent

active

052970906

ABSTRACT:
A static random-access memory is disclosed which utilizes bit line pairs for each column of memory cells for communication of data between external data terminals and the memory cells. A precharge transistor is connected between each bit line and a precharge voltage, for example V , and an equilibration transistor is connected between the bit lines in each bit line pair. The precharge and equilibration transistors are controlled according to selection of the column, so that all columns which are not selected by the column address are precharged and equilibrated, including the unselected columns in the same sub-array as the selected columns. In an additional embodiment of the invention, a data transition detection circuit also controls the precharge and equilibration transistors, so that the precharge and equilibration transistors for the selected columns are turned on responsive to an input data transition during a write operation; this assists the write drivers in more quickly writing the new data onto the bit lines.

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