MRAM cell structure

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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Details

C438S625000, C257S296000, C257S758000, C257SE27084, C257SE27086, C257SE21614, C257SE21645

Reexamination Certificate

active

08080471

ABSTRACT:
Disclosed herein is an improved memory device, and related methods of manufacturing, wherein the area occupied by a conventional landing pad is significantly reduced to around 50% to 10% of the area occupied by conventional landing pads. This is accomplished by removing the landing pad from the cell structure, and instead forming a conductive via structure that provides the electrical connection from the memory stack or device in the structure to an under-metal layer. By forming only this via structure, rather than separate vias formed on either side of a landing pad, the overall width occupied by the connective via structure from the memory stack to an under-metal layer is substantially reduced, and thus the via structure and under-metal layer may be formed closer to the memory stack (or conductors associated with the stack) so as to reduce the overall width of the cell structure.

REFERENCES:
patent: 6956765 (2005-10-01), Saito et al.
patent: 6977181 (2005-12-01), Raberg
patent: 2004/0004889 (2004-01-01), Asao et al.
patent: 2005/0232006 (2005-10-01), Iwata
patent: 200627613 (2006-08-01), None
Taiwanese patent application No. 096127979 office action dated Jan. 5, 2011.

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