Semiconductor device having plural clock domains which...

Details Semiconductor device having plural clock domains which... Semiconductor device having plural clock domains which...

2009-10-08

2011-11-08

Gaffin, Jeffrey A (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S730000, C714S731000

Reexamination Certificate

active

08055964

ABSTRACT:
A semiconductor device, includes a plurality of scan chains for testing a plurality of clock domains whose operating frequencies are different from one another, each of the plurality of scan chains including a plurality of flip-flop circuits, a clock oscillator which generates a plurality of clock signals corresponding to respective operating frequencies that are used to test the plurality of clock domains, a scan clock signal input circuit which receives, from an outside, and a scan clock signal that is supplied to the plurality of scan chains. The semiconductor device further includes a pulse generation circuit unit which generates a clock pulse signal used for the testing based on the clock signal and the scan clock signal, the pulse generation circuit unit including a plurality of pulse generation circuits corresponding to respective operating frequencies, a clock control circuit unit which selectively activates a part of the pulse generation circuit in the pulse generation circuit unit, the clock control circuit including a plurality of logic circuits corresponding to the plurality of scan chains, respectively, and a clock control signal generation unit which generates a clock control signal to control the clock control circuit unit, based on the scan clock signal.

REFERENCES:
patent: 7134061 (2006-11-01), Agashe et al.
patent: 2006/0026476 (2006-02-01), Nishida
patent: 2006-38743 (2006-02-01), None
Kwang-Ting Cheng, Partial Scan Designs Without Using a Separate Scan Clock, 1995, IEEE.

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