Pattern generator and memory testing device using the same

Details Pattern generator and memory testing device using the same Pattern generator and memory testing device using the same

2008-05-21

2011-12-06

Chase, Shelly A (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

08074134

ABSTRACT:
An address operation circuit generates a row address which indicates an address in memory under test to be accessed. The row address memory stores the row addresses generated by the address operation circuit in increments of banks. A memory control signal that includes a bank address to be applied to the memory under test, and which is generated according to a pattern program, is used as a save address to be used to write the row address to the row address memory, and as a load address to be used to read out the row address from the row address memory.

REFERENCES:
patent: 4958346 (1990-09-01), Fujisaki
patent: 6285962 (2001-09-01), Hunter
patent: 6363022 (2002-03-01), Tsuto
patent: 6834361 (2004-12-01), Abbott
patent: 52-063632 (1977-05-01), None
patent: 04-62646 (1992-02-01), None
patent: 05-053550 (1993-03-01), None

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