Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1997-10-16

1999-03-02

Nguyen, Viet Q.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

327107, 327191, 327 53, G06F 1300, H03F 340

Patent

active

058779892

ABSTRACT:
A semiconductor memory device capable of reducing a delay in the conversion of an input chip enable signal having a TTL level, providing a quick chip enable access and avoiding an increase in current consumption even when the quick chip enable access is made possible. The semiconductor memory device in one embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level and having a plurality of transistors whose gate widths are set to first dimensions and a second input buffer activated in response to both an input signal having a TTL level other than the chip enable and the signal having the CMOS level and having a plurality of transistors whose gate widths are set to second dimensions smaller than the first dimensions. Further, a semiconductor memory device in another embodiment includes an input buffer outputting a signal having a CMOS level in response to a chip enable signal having a TTL level and having a plurality of transistors whose gate widths are set to first dimensions and a second input buffer activated in response to both an input signal having a TTL level other than the chip enable signal and the signal having the CMOS level and having a plurality of transistors whose gate widths are set to second dimensions smaller than the first dimensions.

REFERENCES:
patent: 5266848 (1993-11-01), Nakagone et al.
patent: 5398318 (1995-03-01), Hiraishi et al.
patent: 5500614 (1996-03-01), Egawa
patent: 5557221 (1996-09-01), Taguchi et al.
patent: 5629640 (1997-05-01), Egawa
patent: 5699301 (1997-12-01), Egawa

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