Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2009-01-22
2011-11-01
Garber, Charles (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S308000
Reexamination Certificate
active
08048750
ABSTRACT:
The invention provides a method of fabricating a semiconductor device that enhances the amount of stress that is transmitted to the channel region for carrier mobility enhancement. In one embodiment an amorphous region is formed at or near the gate dielectric interface prior to source/drain anneal. In a second embodiment the gate material is amorphous as deposited and processing temperatures are kept below the gate material crystallization temperature until stress enhancement processing has been completed. The amorphous gate material deforms during high temperature anneal and converts from an amorphous to a polycrystalline phase allowing more stress to be transmitted into the channel region. This enhances carrier mobility and improves transistor drive current.
REFERENCES:
patent: 5731239 (1998-03-01), Wong et al.
patent: 6582995 (2003-06-01), Hsieh et al.
patent: 7052946 (2006-05-01), Chen et al.
patent: 2005/0236667 (2005-10-01), Goto et al.
patent: 2007/0281413 (2007-12-01), Li et al.
patent: 2008/0113480 (2008-05-01), Nishida et al.
patent: 2008/0135873 (2008-06-01), Fiorenza et al.
Wang, G.H. et al, “Silicon-Germanium-Tin (SiGeSn) Source and Drain Stressors formed by Implant and Laser Annealing for Strained Silicon-Germanium Channel P-MOSFETs” ; Dec. 2007 Electron Devices Meeting, 2007 IEEE International, p. 131-134.
Xin Wang and J. Wu, “Progress in Modeling of SMT ‘Stress Memorization Technique’ and Prediction of Stress Enhancement by a Novel PMOS SMT Process,” IEEE Xplore, pp. 117-120.
Xin Wang and J. Wu, “Progress in Modeling of SMT ‘Stress Memorization Technique’ and Prediction of Stress Enhancement by a Novel PMOS SMT Process,” IEEE Xplore, pp. 117-120, Sep. 11, 2008 International Conference on Simulation of Semiconductor Processes and Devices.
Wang Xin
Wu Zhiqiang
Brady III Wade J.
Garber Charles
Garner Jacqueline J.
Junge Bryan
Telecky , Jr. Frederick J.
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