Serial interface device built-in self test

Details Serial interface device built-in self test Serial interface device built-in self test

2008-12-30

2011-11-01

Gaffin, Jeffrey A (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S030000, C714S705000, C714S716000, C714S717000, C714S734000, C714S739000, C714S745000, C714S706000, C714S820000

Reexamination Certificate

active

08051350

ABSTRACT:
A built-in self test circuit includes a pattern generator, an elastic buffer, a symbol detector, and a comparison unit. A pattern generator generates a first test pattern to test a port under test and then a result pattern is gotten and stored in the elastic buffer. The symbol detector detects if a starting symbol exists in the test result pattern. If it exists, a second test pattern is generated to be compared with the test result pattern. As a result, a reliability of data transmission of the port under test is determined.

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Intel Corporation, PHY Interface for the PCI Express Architecture, Jun. 19, 2003, version 1.0, pp. 1-31.

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