Compare circuit receiving scan register and inverted clock...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C714S729000, C714S734000

Reexamination Certificate

active

08046651

ABSTRACT:
The disclosure describes a novel method and apparatus for providing expected data, mask data, and control signals to scan test architectures within a device using the falling edge of a test/scan clock. The signals are provided on device leads that are also used to provide signals to scan test architectures using the rising edge of the test/scan clock. According to the disclosure, device test leads serve to input different test signals on the rising and falling edge of the test/scan clock which reduces the number of interconnects between a tester and the device under test.

REFERENCES:
patent: 5740182 (1998-04-01), Narain
patent: 5828579 (1998-10-01), Beausang
patent: 5872793 (1999-02-01), Attaway et al.
patent: 5898702 (1999-04-01), Narayanan et al.
patent: 6763488 (2004-07-01), Whetsel
patent: 6769080 (2004-07-01), Whetsel
patent: 6853212 (2005-02-01), Chandar et al.
patent: 7051257 (2006-05-01), Whetsel
patent: 7613972 (2009-11-01), Takeoka et al.
patent: 7739568 (2010-06-01), Bertanzetti
patent: 2005/0055615 (2005-03-01), Agashe et al.
patent: 2006/0095819 (2006-05-01), Bhatia
patent: 2009/0240997 (2009-09-01), Hasegawa
Hobbs, E.D.; , “Practical considerations for designing ASICs which incorporate scan path and JTAG techniques,” Automated Testing and Software Solutions, IEE Colloquium on , vol., No., pp. 9/1-9/4, Apr. 8, 1992 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=168147&isnumber=4347.
Lofstrom, K.; , “Early capture for boundary scan timing measurements,” Test Conference, 1996. Proceedings., International , vol., No., pp. 417-422, Oct. 20-25, 1996 doi: 10.1109/TEST.1996.557045 URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=557045&isnumber=12091.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Compare circuit receiving scan register and inverted clock... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Compare circuit receiving scan register and inverted clock..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Compare circuit receiving scan register and inverted clock... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4281722

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.