Semiconductor buffer architecture for III-V devices on...

Details Semiconductor buffer architecture for III-V devices on... Semiconductor buffer architecture for III-V devices on...

2010-10-29

2011-10-11

Vu, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C257S014000, C257SE21403, C257SE21407

Reexamination Certificate

active

08034675

ABSTRACT:
A composite buffer architecture for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108cm−2to be formed on silicon substrates. In an embodiment of the present invention, a dual buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations and provide electrical isolation. In an embodiment of the present invention, the material of each buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a GaSb/AlSb buffer is utilized to form an InSb-based quantum well transistor on a silicon substrate.

REFERENCES:
patent: 4872046 (1989-10-01), Morkoc et al.
patent: 5144378 (1992-09-01), Hikosaka
patent: 5495115 (1996-02-01), Kudo et al.
patent: 5883564 (1999-03-01), Partin
patent: 5981400 (1999-11-01), Lo
patent: 6117697 (2000-09-01), Seaford et al.
patent: 6133593 (2000-10-01), Boos et al.
patent: 6320212 (2001-11-01), Chow
patent: 6406795 (2002-06-01), Hwang et al.
patent: 7485503 (2009-02-01), Brask et al.
patent: 2002/0093332 (2002-07-01), Schroeder et al.
patent: 2005/0040429 (2005-02-01), Uppal
patent: 2005/0287752 (2005-12-01), Nouri
patent: 2008/0032478 (2008-02-01), Hudait et al.
patent: 2005-085916 (2005-03-01), None
patent: WO-91/06976 (1991-05-01), None
Office Action from U.S. Appl. No. 11/501,253 mailed May 14, 2008, 12 pages.
Office Action from U.S. Appl. No. 11/501,253 mailed Dec. 12, 2008, 8 pages.
Notice of Allowance from U.S. Appl. No. 11/501,253 mailed Apr. 7, 2009, 4 pages.
Office Action from U.S. Appl. No. 11/498,901 mailed Aug. 1, 2008, 11 pages.
Final Office Action from U.S. Appl. No. 11/498,901 mailed Nov. 17, 2008, 16 pages.
Office Action from U.S. Appl. No. 11/498,901 mailed Jun. 8, 2009, 8 pages.
Final Office Action from U.S. Appl. No. 11/498,901 mailed Dec. 17, 2009, 11 pages.
Office Action from U.S. Appl No. 11/498,901 mailed Mar. 26, 2010, 12 pages.
Final Office Action for U.S. Appl. No. 11/498,685 mailed May 26, 2010, 10 pages.
Office Action for U.S. Appl. No. 11/498,685 mailed Nov. 24, 2009, 9 pages.
Notice of Allowance for U.S. Appl. No. 11/498,685 mailed Aug. 6, 2010, 7 pages.
Uchida et al., “Reduction of Disclocation Density by Thermal Annealing for GaAs/GaSb/Si Heterostructure,” Journal of Crystal Growth, 150, 1995, pp. 681-684.
Balakrishnan, G., et al., “Room-Temperature Optically-Pumped InGaSb Quantum Well Lasers Monolithically Grown on Si (100) Substrate”, IEEE 2005, Feb. 12, 2005, 2 pages.
Datta, et al., US Patent Application, Extreme High Mobility CMOS Logic, U.S. Appl. No. 11/305,452, Dec. 15, 2005.
Kuruvilla, B. A., et al., “Passivation of GaAs (100) using Selenium Sulfide”, 1993 American Institute of Physics, J. Appl. Phys. 73 (9), May 1, 1993, pp. 4384-4387.
Mori, M., et al., “Heteroepitaxial Growth of InSb on a Si (0 0 1) Substrate Via AlSb Buffer Layer”, Applied Surface Science 216, 2003, pp. 569-574.
Nguyen, et al., “Growth of Heteroepitaxial GaSb thn films on Si (100) Substrates,” Journal of Materials Research, vol. 19, No. 8, Aug. 2004, pp. 2315-2321.
Scholz, S., et al., “MOVPE Growth of GaAs on Ge Aubstrates by Inserting a Thin Low Temperature Buffer Layer,” Cryst. Res. Technol. 41, No. 2, (2006), Jan. 15, 2006, pp. 111-116.
Sieg, R.M., et al., “Toward Device-Quality GaAs Growth by Molecular Beam Epitaxy on Offcut Ge/Si—Ge/Si Substrates”, J. Vac. Sci. Technol. B, vol. 16, No. 3, May/Jun. 1998, pp. 1471-1474.
Wan, A.., et al., “Characterization of GaAs Grown by Molecular Beam Epitaxy on Vicinal Ge(100) Substrates”, J. Vac. Sci. Technol. B, vol. 22, No. 4, Jul./Aug. 2004, 6 pages, Jul. 27, 2004, pp. 1893-1898.

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