Memory system and command handling method

Details Memory system and command handling method Memory system and command handling method

2007-09-27

2011-10-11

Rizk, Sam (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S752000

Reexamination Certificate

active

08037390

ABSTRACT:
A memory system including a memory controller and a memory and a related method are disclosed. The method includes communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory, decoding the command and executing an EDC operation related to the EDC data in parallel, and if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else immediately executing an operation indicated by the command without regard to completion of the EDC operation.

REFERENCES:
patent: 5216672 (1993-06-01), Tatosian et al.
patent: 05023395 (1993-02-01), None
patent: 05222495 (1993-08-01), None
patent: 1019980033007 (1998-07-01), None

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