Method of fabricating memory

Details Method of fabricating memory Method of fabricating memory

2010-08-06

2011-10-25

Pham, Hoai V (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S211000, C438S593000, C257SE21179

Reexamination Certificate

active

08043908

ABSTRACT:
A method of fabricating a semiconductor device is provided. First, a stacked structure is formed on a substrate. The stacked structure includes, from the substrate, a dielectric layer and a conductive gate in order. An ion implant process is performed to form doped regions in the substrate on the opposite sides of the stacked structure. Thereafter, source-side spacer is formed on a sidewall of the stacked structure. A thermal process is performed to activate the doped regions, thereby forming a source in the substrate under the sidewall of the stacked structure having the source-side spacer and a drain in the substrate on another side of the stacked structure.

REFERENCES:
patent: 5897354 (1999-04-01), Kachelmeier
Hang-Ting Lue et al., “BE-SONOS: A Bandgap Engineered SONOS with Excellent Performance and Reliability” Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, Dec. 2005.
Chinese Examination Report of Taiwan Application No. 096120710, dated Aug. 30, 2010.

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