Nonvolatile memory device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S200000, C257S240000, C257SE21680, C257SE21689, C257SE21691, C257SE27016, C257SE27081, C257SE21087, C257SE27040, C438S003000, C438S257000, C438S261000, C438S264000, C438S267000

Reexamination Certificate

active

08080842

ABSTRACT:
Disclosed is a nonvolatile memory device with cell and peripheral circuit regions confined on a substrate. Cell gate electrodes are arranged in the cell region while peripheral gate electrodes are arranged in the peripheral-circuit region. Each cell gate electrode includes stacked conductive and semiconductor layers, but the peripheral gate electrode includes stacked semiconductor layers. The conductive layer of the cell gate electrode is different from the lowest semiconductor layer of the peripheral gate electrode in material, which can improve characteristics of memory cells and peripheral transistors without causing mutual interference with each other.

REFERENCES:
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patent: 7399672 (2008-07-01), Lee et al.
patent: 2002/0137287 (2002-09-01), Takebuchi
patent: 2003/0011017 (2003-01-01), Lee et al.
patent: 2003/0030097 (2003-02-01), Lee et al.
patent: 2003/0042532 (2003-03-01), Forbes
patent: 2003/0080387 (2003-05-01), Cho et al.
patent: 2004/0014323 (2004-01-01), Shimizu
patent: 2004/0212019 (2004-10-01), Shinohara et al.
patent: 2005/0088889 (2005-04-01), Lee et al.
patent: 2005/0093047 (2005-05-01), Goda et al.
patent: 2006/0261401 (2006-11-01), Bhattacharyya
patent: 2003-347511 (2003-12-01), None
patent: 2004-039866 (2004-02-01), None
patent: 10-0318148 (2002-04-01), None

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