Semiconductor memory device and method of defective cell...

Details Semiconductor memory device and method of defective cell... Semiconductor memory device and method of defective cell...

2008-10-27

2011-11-01

Tran, Andrew Q (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S203000, C365S208000, C365S210130, C365S230060, C365S185150, C365S189070, C365S189090

Reexamination Certificate

active

08050123

ABSTRACT:
A semiconductor memory device simultaneously selects an object cell and a counter cell which connect with a common bit line, simultaneously activates sub-word lines of the object cell and the counter cell after predetermined levels are written in the object cell and the counter cell, simultaneously read data of the object cell and the counter cell from the common bit line, and hence, determines whether the object cell is normal or defective, based on a voltage level of the common bit line. Thereby, the defective cell in the semiconductor memory device can be reliably detected.

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patent: 2006-260735 (2006-09-01), None

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