Semiconductor device and method of fabricating the same

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S069000, C257S365000, C257S401000, C257S411000

Reexamination Certificate

active

07829953

ABSTRACT:
A semiconductor device includes a semiconductor substrate including an NMOS region and a PMOS region, a gate insulating layer formed on the semiconductor substrate, an NMOS gate formed on the gate insulating layer of the NMOS region, and a PMOS gate formed on the gate insulating layer of the PMOS region. Any one of the NMOS gate and the PMOS gate includes a one-layered conductive layer pattern, and another of the NMOS gate and the PMOS gate includes a three-layered conductive layer pattern.

REFERENCES:
patent: 6696345 (2004-02-01), Chau et al.
patent: 6790719 (2004-09-01), Adetutu
patent: 6794234 (2004-09-01), Polishchuk et al.
patent: 7019351 (2006-03-01), Eppich
patent: 2004/0023478 (2004-02-01), Samavedam et al.
patent: 2005/0250258 (2005-11-01), Metz et al.
patent: 2008/0029821 (2008-02-01), Yamagami et al.
patent: 2008/0157212 (2008-07-01), Lavoie et al.
patent: 10323013 (2003-11-01), None
patent: 1020020080111 (2002-10-01), None
patent: 1020060083337 (2006-07-01), None
U.S. Patent Application Publication US2003/0203560 A1 corresponds and serves as the English translation for Foreign Reference DE103 23 013 A1.
English Abstract Publication No. 1020060083337.
English Abstract Publication No. 1020020080111.

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