Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Flip chip
Reexamination Certificate
2003-11-21
2010-06-01
Purvis, Sue (Department: 2893)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Flip chip
C257SE21503, C438S015000, C438S108000
Reexamination Certificate
active
07728439
ABSTRACT:
The reliabilities of a wiring substrate and a semiconductor apparatus are improved by reducing the internal stress caused by the difference of thermal expansion coefficients between a base substrate and a semiconductor chip. A wiring layer (5) is provided on one surface of a silicon base (3). An electrode as the uppermost layer of the wiring layer (5) is provided with an external bonding bump (7). A through-electrode (4) is formed in the base (3) for electrically connecting the wiring layer (5) and an electrode terminal. The electrode terminal on the chip mounting surface is bonded to an electrode terminal of a semiconductor chip (1) by an internal bonding bump (6). The thermal expansion coefficient of the silicon base (3) is equivalent to that of the semiconductor chip (1) and not more than that of the wiring layer (5).
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Japanese Patent Office issued a Japanese Office Action, Application No. 2004-553229.
Nishiyama Tomohiro
Tago Masamoto
Harrison Monica D
NEC Corporation
Purvis Sue
Young & Thompson
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