Split gate memory cell and method therefor

Details Split gate memory cell and method therefor Split gate memory cell and method therefor

2008-10-20

2010-06-08

Hoang, Quoc D (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S316000, C257SE21681

Reexamination Certificate

active

07732278

ABSTRACT:
A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.

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