DRAM layout with vertical FETS and method of formation

Details DRAM layout with vertical FETS and method of formation DRAM layout with vertical FETS and method of formation

2005-10-25

2010-06-15

Dang, Trung (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S270000, C438S272000, C257SE21410, C257SE21442

Reexamination Certificate

active

07736969

ABSTRACT:
DRAM cell arrays having a cell area of about 4F2comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.

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