Hybrid Schottky source-drain CMOS for high mobility and low...

Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With specified crystal plane or axis

Reexamination Certificate

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C257SE33003, C438S168000

Reexamination Certificate

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07737532

ABSTRACT:
A CMOS device is provided. A semiconductor device comprises a substrate, the substrate having a first region and a second region, the first region having a first crystal orientation represented by a family of Miller indices comprising {i,j,k}, the second region having a second crystal orientation represented a family of Miller indices comprising {l,m,n}, wherein l2+m2+n2>i2+j2+k2. Alternative embodiments further comprise an NMOSFET formed on the first region, and a PMOSFET formed on the second region. Embodiments further comprise a Schottky contact formed with at least one of a the NMOSFET or PMOSFET.

REFERENCES:
patent: 4857986 (1989-08-01), Kinugawa
patent: 5384473 (1995-01-01), Yoshikawa et al.
patent: 6096590 (2000-08-01), Chan et al.
patent: 6261932 (2001-07-01), Hulfachor
patent: 6744103 (2004-06-01), Snyder
patent: 6784035 (2004-08-01), Snyder et al.
patent: 6911383 (2005-06-01), Doris et al.
patent: 7235433 (2007-06-01), Waite et al.
patent: 7298009 (2007-11-01), Yan et al.
patent: 2004/0041226 (2004-03-01), Snyder et al.
patent: 2004/0113171 (2004-06-01), Chiu et al.
patent: 2004/0266076 (2004-12-01), Doris et al.
patent: 2005/0003595 (2005-01-01), Snyder et al.
Connelly, D., et al., “A New Route to Zero-Barrier Metal Source/Drain MOSFETs,” IEEE Transactions on Nanotechnology, Mar. 2004, pp. 98-104, vol. 3, No. 1.
Connelly, D., at al., “Optimizing Schottky S/D Offset for 25-nm Dual-Gate CMOS Performance,” IEEE Electron Device Letters, Jun. 2003, pp. 411-413, vol. 24, No. 6.
Connelly, D. et al., “Performance Advantage of Schottky Source/Drain in Ultrathin-Body Silicon-on-Insulator and Dual-Gate CMOS,” IEEE Transactions in Electron Devices, May 2003, pp. 1340-1345, vol. 50, No. 5.
Doris, B., et al., “A Simplified Hybrid Orientation Technology (SHOT) for High Performance CMOS,” Symposium on VLSI Technology Digest of Technical Papers, IEEE, 2004, pp. 86-87.
Hwang, J. R., et al., “Symmetrical 45nm PMOS on (110) Substrate with Excellent S/D Extension Distribution and Mobility Enhancement,” Symposium on VLSI Technology Digest of Technical Papers, IEEE, 2004, pp. 90-91.
Kedzierski, J., et al., “Complementary silicide source/drain thin-body MOSFETs for the 20nm gate length regime,” IEDM, 2000, pp. 57-60.
Kinoshita, a., et al., “Solution for High-Performance Schottky-Source/Drain MOSFETs: Schottky Barrier Height Engineering with Dopant Segregation Technique,” Symposium on VLSI Technology Digest of Technical Papers, IEEE, 2004, pp. 168-169.
Lin, H.-C., et al., “High-Performance P-Channel Schottky-Barrier SOI FinFET Featuring Self-Aligned PtSi Source/Drain and Electrical Junctions,” IEEE Electron Device Letters, Feb. 2003, pp. 102-104, vol. 24, No. 2.
Sullivan, J. P. et al., “Correlation of the interfacial structure and electrical properties of epitaxial silicides on Si,” J. Vac. Sci. Technol., American Vacuum Society, Jul./Aug. 1992, pp. 1959-1964, vol. A 10, No. 4.
Tung, R. T., et al., “Expitaxial metal-semiconductor structures and their properties,” J. Vac. Sci. Technol., American Vacuum Society, Nov./Dec. 1986, pp. 1435-1443, vol. B 4, No. 6.
Tung, R. T., et al., “Schottky-barrier heights of single-crystal NiSi2on Si(111): The effect of a surfacep-njunction,” Physical Review, The American Physical Society, May 15, 1986, pp. 7077-7090, vol. 33, No. 10.
Tung, R. T., et al., “Schottky-Barrier Inhomogeneity at Epitaxial NiSi2Interfaces on Si(100),” Physical Review Letters, Jan. 7, 1991, pp. 72-75, vol. 66, No. 1.
Werner, P., et al., “Interface structure and Schottky barrier height of buried CoSi2/Si(001) layers,” J. Appl. Phys., American Institute of Physics, Sep. 15, 1993, pp. 3846-3854, vol. 74, No. 6.
Yang, F.-L., et al., “5nm-Gate Nanowire FinFET,” Symposium on VLSI Technology Digest of Technical Papers, IEEE, 2004, pp. 196-197.
Yang, M., et al., “On the Integration of CMOS and Hybrid Crystal Orientations,” Symposium on VLSI Technology Digest of Technical Papers, IEEE, 2004, pp. 160-161.
Liu, C.W., et al., “Mobility-Enhancement Technologies,” IEEE Circuits & Devices Magazine, May/Jun. 2005, pp. 21-36.
Michaelson, H.B., “The work function of the elements and its periodicity,” Journal of Applied Physics, vol. 48, No. 11, Nov. 1977, pp. 4729-4733.

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