Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1997-01-17
1999-03-02
Niebling, John F.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438305, 438592, 438772, H01L 21336
Patent
active
058770577
ABSTRACT:
A semiconductor process in which a low temperature oxidation of a semiconductor substrate upper surface followed by an in situ deposition of polysilicon are used to create a thin oxide MOS structure. Preliminarily, the upper surface of a semiconductor substrate is cleaned, preferably with a standard RCA clean procedure. A gate dielectric layer is then formed on the upper surface of the substrate. A first polysilicon layer is then in situ deposited on the gate dielectric layer. An upper portion of the first polysilicon layer is then oxidized and the oxidized portion is thereafter removed from the upper surface of the first polysilicon layer. A second polysilicon layer is subsequently deposited upon the first polysilicon layer. Preferably, the formation of the gate dielectric on the semiconductor substrate upper surface comprises annealing the semiconductor substrate in an ambient comprising an inert species and O.sub.2. The ambient temperature of the first oxidation chamber is preferably maintained at a temperature less than approximately 300.degree. C. during the formation of the gate dielectric. The first polysilicon layer, in the preferred embodiment, is deposited in situ such that the semiconductor substrate remains within the first oxidation chamber during the deposition of the first polysilicon layer. The oxidation of an upper portion of the first polysilicon layer is preferably accomplished in a nitrogen bearing ambient so that nitrogen is introduced into the first polysilicon layer to inhibit the penetration of mobile impurities across the gate dielectric into the channel region of the transistor and enhance the device properties.
REFERENCES:
patent: 4776925 (1988-10-01), Fossum et al.
patent: 4897368 (1990-01-01), Kobushi et al.
patent: 4914046 (1990-04-01), Tobin et al.
patent: 5296411 (1994-03-01), Gardner et al.
patent: 5316981 (1994-05-01), Gardner et al.
patent: 5330935 (1994-07-01), Dobuzinsky et al.
patent: 5332692 (1994-07-01), Saitoh
patent: 5350698 (1994-09-01), Huang et al.
patent: 5360769 (1994-11-01), Thakur et al.
patent: 5393676 (1995-02-01), Anjum et al.
patent: 5397720 (1995-03-01), Kwong et al.
patent: 5468974 (1995-11-01), Aronowitz et al.
patent: 5538923 (1996-07-01), Gardner et al.
patent: 5541141 (1996-07-01), Cho
patent: 5567638 (1996-10-01), Lin et al.
patent: 5633177 (1997-05-01), Anjum
patent: 5652166 (1997-07-01), Sun et al.
patent: 5674788 (1997-10-01), Wristers et al.
patent: 5700699 (1997-12-01), Han et al.
Wolf, Stanley, Ph.D., Silicon Processing for the VLSI Era, vol. 1 : Process Technology, 1986, p. 183.
Wolf, Stanley, Ph.D., Silicon Processing for the VLSI Era, vol. 3: The Submicron Mosfet, 1995, p. 438.
Ghandhi, "VLSI Fabrication Principles Silicon and Gallium Arsenide", John Wiley and Sons, pp. 639-642, 1994.
Gardner Mark I.
Gilmer Mark C.
Advanced Micro Devices , Inc.
Booth Richard A.
Daffer Kevin L.
Kowert Robert C.
Niebling John F.
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