Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate
2006-10-30
2010-10-19
Britt, Cynthia (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Replacement of memory spare location, portion, or segment
C714S723000
Reexamination Certificate
active
07818636
ABSTRACT:
A memory circuit comprises a first memory that stores data in a plurality of memory locations that are associated with memory addresses. A memory interface communicates with said first memory. A second memory communicates with said memory interface and stores memory addresses of defective memory locations that are identified in said first memory.
REFERENCES:
patent: 4205301 (1980-05-01), Hisazawa
patent: 4901360 (1990-02-01), Shu et al.
patent: 4903268 (1990-02-01), Hidaka et al.
patent: 5056095 (1991-10-01), Horiguchi et al.
patent: 5127014 (1992-06-01), Raynham
patent: 5475825 (1995-12-01), Yonezawa et al.
patent: 5485595 (1996-01-01), Assar et al.
patent: 5491703 (1996-02-01), Barnaby et al.
patent: 5513135 (1996-04-01), Dell et al.
patent: 5535226 (1996-07-01), Drake et al.
patent: 5636354 (1997-06-01), Lear
patent: 5758056 (1998-05-01), Barr
patent: 5796758 (1998-08-01), Levitan
patent: 5848076 (1998-12-01), Yoshimura
patent: 5958068 (1999-09-01), Arimilli et al.
patent: 5958079 (1999-09-01), Yoshimura
patent: 5959914 (1999-09-01), Gates et al.
patent: 5973949 (1999-10-01), Kramer et al.
patent: 6000006 (1999-12-01), Bruce et al.
patent: 6041422 (2000-03-01), Deas
patent: 6058047 (2000-05-01), Kikuchi
patent: 6065141 (2000-05-01), Kitagawa
patent: 6067656 (2000-05-01), Rusu et al.
patent: 6085334 (2000-07-01), Giles et al.
patent: 6134631 (2000-10-01), Jennings
patent: 6175941 (2001-01-01), Poeppelman et al.
patent: 6233646 (2001-05-01), Hahm
patent: 6237116 (2001-05-01), Fazel et al.
patent: 6275406 (2001-08-01), Gibson et al.
patent: 6295617 (2001-09-01), Sonobe
patent: 6385071 (2002-05-01), Chai et al.
patent: 6414876 (2002-07-01), Harari et al.
patent: 6438726 (2002-08-01), Walters, Jr.
patent: 6457154 (2002-09-01), Chen et al.
patent: 6484271 (2002-11-01), Gray
patent: 6563754 (2003-05-01), Lien et al.
patent: 6700827 (2004-03-01), Lien et al.
patent: 6751755 (2004-06-01), Sywyk et al.
patent: 6778457 (2004-08-01), Burgan
patent: 6799246 (2004-09-01), Wise et al.
patent: 6898140 (2005-05-01), Leung et al.
patent: 7017089 (2006-03-01), Huse
patent: 7051151 (2006-05-01), Perego et al.
patent: 7062597 (2006-06-01), Perego et al.
patent: 7065622 (2006-06-01), Donnelly et al.
patent: 7073099 (2006-07-01), Sutardja et al.
patent: 7216284 (2007-05-01), Hsu et al.
patent: 7308530 (2007-12-01), Armstrong et al.
patent: 2001/0048625 (2001-12-01), Patti et al.
patent: 2004/0218439 (2004-11-01), Harrand et al.
patent: 2004/0243886 (2004-12-01), Klein
patent: 2006/0158950 (2006-07-01), Klein
patent: 2008/0307301 (2008-12-01), Decker et al.
“Functional testing of content-addressable memories” by Lin et al. This paper appears in: Memory Technology, Design and Testing, 1998. Proceedings. International Workshop on Publication Date: Aug. 24-25, 1998 On pp. 70-75 ISBN: 0-8186-8494-1 INSPEC Accession No. 6142197.
“Testing and diagnosing embedded content addressable memories” by Li et al. This paper appears in: VLSI Test Symposium, 2002. Proceedings 20th IEEE Publication Date: Apr. 28, 2002-May 2, 2002 On pp. 389-394 ISBN: 0-7695-1570-3 INSPEC Accession No. 7361019.
“Fully-parallel multi-megabit integrated CAM/RAM design” by Schultz et al. This paper appears in: Memory Technology, Design and Testing, 1994., Records of the IEEE International Workshop on Publication Date: Aug. 8-9, 1994 On pp. 46-51 ISBN: 0-8186-6245-X INSPEC Accession No. 4933182.
“Fault-tolerant content addressable memory” by Lo, J.-C. This paper appears in: Computer Design: VLSI in Computers and Processors, 1993. ICCD '93. Proceedings., 1993 IEEE International Conference on Publication Date: Oct. 3-6, 1993 On pp. 193-196 ISBN: 0-8186-4230-0 INSPEC Accession No. 4955866.
“Mapping and repairing embedded-memory defects” by Youngs et al. This paper appears in: Design & Test of Computers, IEEE Publication Date: Jan.-Mar. 1997 vol. 14, Issue: 1 On page(s): 18-24 ISSN: 0740-7475 INSPEC Accession Number: 5522644.
“Design rule centring for row redundant content addressable memories” by Noghani et al. This paper appears in: Defect and Fault Tolerance in VLSI Systems, 1992. Proceedings., 1992 IEEE International Workshop on Publication Date: Nov 4-6, 1992 on pp. 217-226 ISBN: 0/8186-2837-5 INSPECAccession Number: 4432479.
“A self-testing reconfigurable CAM” McAuley et al. This paper appears in: Solid-State Circuits, IEEE Journal of Publication Date: Mar. 1991 vol. 26, Issue: 3 on pp. 257-261 Inspec Accession Number: 3911418.
“FBDIMM—Unleashing Server Memory Capacity”; Micron Technology, Inc.; 2006; 2 pages.
Bigger, Better, Faster . . . Improve server performance with Crucial fully buffered DIMMs; Andy Heidelberg of Crucial Technology; 6 pages.
Notification of Transmittal of The International Search Report and The Written Opinion of The International Searching Authority, or The Declaration dated May 27, 2008 in reference to PCT/US2007/016661 (21 pgs).
“Memory Built-in Self-repair Using Redundant Words” Schober et al. International Test Conference Proceedings. Publication Date: Oct. 30-Nov. 1, 2001 pp. 995-1001 Inspec Accession No. 7211400.
IBM TDB NN85112562 “System for Efficiently Using Spare Memory Components for Defect Corrections Employing Content-Addressable Memory” Date: Nov. 1, 1985.
Azimi Saeed
Sutardja Sehat
Britt Cynthia
Marvell International Ltd.
LandOfFree
Method and apparatus for improving memory operation and yield does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for improving memory operation and yield, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for improving memory operation and yield will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4218788