Dynamic programmable delay selection circuit and method

Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay

Reexamination Certificate

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C713S400000, C713S500000

Reexamination Certificate

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07849346

ABSTRACT:
A controller may include a measurement circuit configured to generate a proxy signal representing delay variations in the controller. The measurement circuit may also generate a measurement value from the proxy signal. A control circuit may be configured to convert the measurement value into a control value. A delay circuit may be adjusted by the control value to alter an amount of delay of a signal.

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patent: 5890100 (1999-03-01), Crayford
patent: 5943206 (1999-08-01), Crayford
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patent: 6160542 (2000-12-01), Hwang
patent: 7164415 (2007-01-01), Ooishi et al.
patent: 7496781 (2009-02-01), Tamura et al.
patent: 2002/0159303 (2002-10-01), Ware et al.
“Double Data Rage Delay Line,” SA 14-2394-00, IBM Microelectronics Division, Dec. 10, 1999, 25 pages.
“DDR SDRAM Functionality and Controller Read Data Capture,” Micron Technology, Inc. DesignLine vol. 8, Issue 3, 1999, 24 pages.

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