Metal gate high-K devices having a layer comprised of...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S392000, C257S410000, C257S412000, C257SE29255, C257SE27062

Reexamination Certificate

active

07847356

ABSTRACT:
Disclosed is a method to fabricate a semiconductor device, and a device fabricated in accordance with the method. The method includes providing a substrate comprised of silicon; performing a shallow trench isolation process to delineate nFET and pFET active areas and, within each active area, forming a gate structure over a surface of the substrate, the gate structure comprising in order from the surface of the substrate, a layer of high dielectric constant oxide, a layer comprised of a metal, a layer comprised of amorphous silicon, and a layer comprised of polycrystalline silicon. The layer comprised of amorphous silicon is provided to substantially prevent regrowth of the high dielectric constant oxide layer in a vertical direction during at least a deposition and processing of the polycrystalline silicon layer and/or metal layer.

REFERENCES:
patent: 7105889 (2006-09-01), Bojarczuk, Jr. et al.
patent: 2005/0087870 (2005-04-01), Adetutu et al.
patent: 2005/0136589 (2005-06-01), Rotondaro et al.
patent: 2006/0246647 (2006-11-01), Visokay et al.
patent: 2006/0246651 (2006-11-01), Chambers et al.
patent: 2007/0122962 (2007-05-01), Chambers et al.
patent: 2007/0152276 (2007-07-01), Arnold et al.
patent: 2009/0085175 (2009-04-01), Clark et al.

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