Integrated circuit with JTAG port, TAP linking module, and...

Details Integrated circuit with JTAG port, TAP linking module, and... Integrated circuit with JTAG port, TAP linking module, and...

2008-01-29

2010-02-09

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S729000

Reexamination Certificate

active

07661049

ABSTRACT:
An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.

REFERENCES:
patent: 5222068 (1993-06-01), Burchard
patent: 6378090 (2002-04-01), Bhattacharya
patent: 6408413 (2002-06-01), Whetsel
patent: 6804725 (2004-10-01), Whetsel
“Hierarchical test access architecture for embedded cores in anintegrated circuit” by Bhattacharya, D. This paper appears in: VLSI Test Symposium, 1998. Proceedings. 16th IEEE Publication Date: Apr. 26-30, 1998 On pp. 8-14 ISBN: 0-8186-8436-4 INSPEC Accession No. 6039765.

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