Self-aligned patterning method by using non-conformal film...

Details Self-aligned patterning method by using non-conformal film... Self-aligned patterning method by using non-conformal film...

2007-04-26

2010-06-08

Le, Thao X (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257SE29300, C257S315000

Reexamination Certificate

active

07732276

ABSTRACT:
A method for fabricating a memory device with a self-aligned trap layer which is optimized for scaling is disclosed. In the present invention, a non-conformal film is deposited over the charge trapping layer to form a thick film on top of the core source/drain region and a pinch off and a void or a narrow channel at the top of the STI trench. An etch is performed on the non-conformal film to open pinch-off or widen the narrow channel in the non-conformal. The trapping layer is then completely or partially etched between the core cells. The non-conformal film is removed. And a top oxide is formed. The top oxide converts the remaining trap layer to oxide if the trapping layer is partially etched and thus isolate the trap layer.

REFERENCES:
patent: 6274901 (2001-08-01), Odake et al.
patent: 7067377 (2006-06-01), Park et al.
patent: 2005/0287763 (2005-12-01), Kim et al.
patent: 2006/0202263 (2006-09-01), Lee
patent: 10 2004 027424 (2005-09-01), None
patent: 95/08840 (1995-03-01), None

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