Method of manufacturing nonvolatile semiconductor memory

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate

Reexamination Certificate

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C257S316000, C257SE21422

Reexamination Certificate

active

07851305

ABSTRACT:
A method of manufacturing a NAND nonvolatile semiconductor memory which involves forming a bit line contact between adjacent select transistors of the NAND nonvolatile semiconductor memory, the method has patterning memory cells and said select transistors of said NAND nonvolatile semiconductor memory; forming a first insulating film between adjacent two of said memory cells, between said memory cells and said select transistors, and between adjacent two of said select transistors; selectively etching the first insulating film between said select transistors to form a side wall spacer on each of said select transistors; forming a second insulating film on said memory cells, said first insulating film between said memory cells, said select transistors and said side wall spacers; forming a resist pattern on said second insulating film; and simultaneously forming an opening in an insulating film and a control gate on a floating gate of each of said select transistors using said resist pattern and an opening between said adjacent select transistors using said resist pattern.

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patent: 6060346 (2000-05-01), Roh et al.
patent: 2004/0178470 (2004-09-01), Hieda
patent: 2005/0082602 (2005-04-01), Okajima
patent: 2006/0038218 (2006-02-01), Yaegashi et al.
patent: 2007/0064496 (2007-03-01), Oh
patent: 2007/0120166 (2007-05-01), Arai et al.
patent: 2002-231835 (2002-08-01), None
patent: 2005-123524 (2005-05-01), None

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