Dynamic random access memory with internal testing switches

Details Dynamic random access memory with internal testing switches Dynamic random access memory with internal testing switches

1995-04-14

1996-09-17

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365201, G11C 700

Patent

active

055575714

ABSTRACT:
In a dynamic random access memory device, first, second and third switches and an internal signal generator therefor are provided besides circuit portions of an ordinary random access memory such as a memory cell. A data input circuit includes data input pins for receiving an input data and data-in-buffers for storing the input data. The first switch can connect one of data input pins to either one of data in buffers or an end of a signal line. The second switch can connect the data-in-buffers to a data output circuit. The third switch can connect the internal voltage supply line to either an internal voltage generator or the other end of the signal line. When a memory is tested, the switch signal generator generates signals so as to make the first switch connect the one of said input pins to the end of the signal line, to make the second switch to connect the data in buffer to the data output circuit, and to make the third switch to connect an internal voltage supply line to the other end of the signal line. Thus, an external voltage can be supplied through one of the data input pins instead of an internal voltage generator, and defective products can be selected out. In an alternative example, the first switch is provided for the data output pins instead of the data input pins.

REFERENCES:
patent: 4899313 (1990-02-01), Kumanoya
patent: 5016220 (1991-05-01), Yamagata
patent: 5208778 (1993-05-01), Kumanoya
patent: 5331596 (1994-07-01), Miyazawa

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