Nonvolatile memory device storing data based on change in...

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Reexamination Certificate

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Details

C365S185120, C365S185220

Reexamination Certificate

active

07835196

ABSTRACT:
A nonvolatile memory device includes a pair of PMOS transistors, and a control circuit configured to operate in a store mode to apply to a first one of the PMOS transistors potentials that cause an NBTI degradation purposefully and to apply to a second one of the PMOS transistors potentials that cause no NBTI degradation while causing no current to flow between a source node and a drain node of the first one of the PMOS transistors, and to operate in a recall mode to set gate nodes of the PMOS transistors to a common potential to detect a difference in the NBTI degradation between said PMOS transistors.

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