Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2008-12-17
2010-06-01
Coleman, W. David (Department: 2823)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S257000, C257SE21249
Reexamination Certificate
active
07727893
ABSTRACT:
In a method of forming a dielectric layer pattern, lower patterns are formed on a substrate. A first dielectric layer is formed on sidewalls and upper surfaces of the lower patterns and a surface of the substrate. A mask pattern is formed on the first dielectric layer to partially expose the first dielectric layer. The exposed first dielectric layer on upper surfaces and upper sidewalls of the lower patterns is partially removed and the removed first dielectric layer is deposited on surfaces of the first dielectric layer between the lower patterns, to form a second dielectric layer having a thickness greater than that of the first dielectric layer. The second dielectric layer on the sidewalls of the lower patterns and the substrate is etched to form a dielectric layer pattern. Accordingly, damage to the underlying layer may be reduced, and an unnecessary dielectric layer may be completely removed.
REFERENCES:
patent: 2006/0091445 (2006-05-01), Utsuno
patent: 2007/0184605 (2007-08-01), Lee
patent: 1020060058812 (2006-06-01), None
patent: 1020070090355 (2007-09-01), None
patent: 784094 (2007-12-01), None
Kim Dong-Hyun
Min Jae-Ho
Coleman W. David
Myers Bigel Sibley & Sajovec P.A.
Samsung Electronics Co,. Ltd.
Scarlett Shaka
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