Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

Reexamination Certificate

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Details

C365S185120, C365S234000, C365S238500

Reexamination Certificate

active

07663937

ABSTRACT:
A semiconductor memory having a plurality of memory cells coupled to bit lines includes a bit line selecting circuit, a latch circuit, and a switching circuit. The bit line selecting circuit is disposed in a cell area where the memory cells are formed. The bit line selecting circuit is configured to select one of the bit lines in response to a first control signal. The latch circuit is disposed in a surrounding circuit area. The latch circuit is configured to perform a program operation or a read operation on the memory cells corresponding to the bit line selected by the bit line selecting circuit. The switching circuit is disposed in the surrounding circuit area, and is coupled between the bit line selecting circuit and the latch circuit. The switching circuit is configured to switch between the bit line selecting circuit and the latch circuit in response to a second control signal.

REFERENCES:
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patent: 6717861 (2004-04-01), Jeong et al.
patent: 6940758 (2005-09-01), Chung
patent: 7173861 (2007-02-01), Cho et al.
patent: 7245533 (2007-07-01), Shibata
patent: 2002-134633 (2002-05-01), None
patent: 1020010061482 (2001-07-01), None
patent: 1020020057687 (2002-07-01), None
patent: 1020050095191 (2005-09-01), None
patent: 1020060104404 (2006-10-01), None

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