Method and mechanism for performing simulation off...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C703S014000

Type

Reexamination Certificate

Status

active

Patent number

07853903

Description

ABSTRACT:
An improved method and mechanism for verification of an electrical circuit design is provided. The method and system simultaneously provides the coverage advantage of formal verification with the scaling efficiencies of simulation. In one approach, the method and system generates an intelligent set of test vectors off a resolution proof. The intelligent set of test vectors can be used to simulate the circuit design for complete coverage without having to test the entire set of possible variable assignments for the CNF formula corresponding to the circuit design.

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