Scan testing using scan frames with embedded commands

Details Scan testing using scan frames with embedded commands Scan testing using scan frames with embedded commands

2007-02-01

2010-02-02

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C324S765010

Reexamination Certificate

active

07657810

ABSTRACT:
Testing of integrated circuits is achieved by a test architecture utilizing a scan frame input shift register, a scan frame output shift register, a test controller, and a test interface comprising a scan input, a scan clock, a test enable, and a scan output. Scan frames input to the scan frame input shift register contain a test stimulus data section and a test command section. Scan frames output from the scan frame output shift register contain a test response data section and, optionally, a section for outputting other data. The command section of the input scan frame controls the test architecture to execute a desired test operation.

REFERENCES:
patent: 7355430 (2008-04-01), Whetsel
patent: 7401277 (2008-07-01), Yamada et al.
patent: 7409612 (2008-08-01), Van De Logt et al.
“Hierarchical test access architecture for embedded cores in anintegrated circuit” by Bhattacharya, D. This paper appears in: VLSI Test Symposium, 1998. Proceedings. 16th IEEE Publication Date: Apr. 26-30, 1998 On pp. 8-14 ISBN: 0-8186-8436-4 INSPEC Accession No. 6039765.
“Test volume reduction via flip-flop compatibility analysis for balanced parallel scan” by Ashouei et al. This paper appears in: Current and Defect Based Testing, 2004. DBT 2004. Proceedings. 2004 IEEE International Workshop on Publication Date: Apr. 25, 2004 On pp. 105-109 ISBN: 0-7803-8950-6 INSPEC Accession No. 8332514.
“A new approach for massive parallel scan design”by Woo Cheol Chung Ha, D.S. This paper appears in: Test Conference, 2005. Proceedings. ITC 2005. IEEE International Publication Date: Nov. 8-8, 2005 On pp. 10 pp. -506 ISBN: 0-7803-9038-5 INSPEC Accession No. 9004567.
IEEE standard test access port and boundary-scan architecture—IEEE Std 1149.1-2001.

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