Non-volatile memory arrays having dual control gate cell...

Details Non-volatile memory arrays having dual control gate cell... Non-volatile memory arrays having dual control gate cell...

2008-01-25

2010-06-15

Dickey, Thomas L (Department: 2893)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S593000, C257SE21680, C257SE21681

Reexamination Certificate

active

07736973

ABSTRACT:
Non-volatile semiconductor memory devices with dual control gate memory cells and methods of forming are provided. A charge storage layer is etched into strips extending across a substrate surface in a row direction with a tunnel dielectric layer therebetween. The resulting strips may be continuous in the row direction or may comprise individual charge storage regions if already divided along their length in the row direction. A second layer of dielectric material is formed along the sidewalls of the strips and over the tunnel dielectric layer in the spaces therebetween. The second layer is etched into regions overlaying the tunnel dielectric layer in the spaces between strips. An intermediate dielectric layer is formed along exposed portions of the sidewalls of the strips and over the second dielectric layer in the spaces therebetween. A layer of control gate material is deposited in the spaces between strips. The resulting control gates are separated from the strips by the intermediate dielectric layer and from the substrate surface by the tunnel dielectric layer, the second layer of dielectric material and the intermediate dielectric layer.

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