Fault tolerant computer

Details Fault tolerant computer Fault tolerant computer

2007-10-30

2010-11-02

Du, Thuan N (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S400000, C714S011000

Reexamination Certificate

active

07827429

ABSTRACT:
A fault tolerant computer comprises a first unit, a second unit, a delay buffer and a delay time setting unit. The first unit executes a computer program in response to an input signal. The second unit executes the computer program in the same execution environment as the first unit in response to the input signal. The delay buffer controls a delay time of a timing when the input signal is input to the first unit with respect to a timing when the input signal is input to the second unit. The delay time setting unit sets the delay time to zero when receiving a synchronization mode signal and sets the delay time to be larger than zero when receiving a delay mode signal.

REFERENCES:
patent: 6141770 (2000-10-01), Fuchs et al.
patent: 2004/0153857 (2004-08-01), Yamazaki et al.
patent: 2005165599 (2005-06-01), None

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