Integrated circuit test using clock signal modification

Details Integrated circuit test using clock signal modification Integrated circuit test using clock signal modification

2008-11-06

2010-06-22

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S744000, C326S093000

Reexamination Certificate

active

07743300

ABSTRACT:
An integrated circuit includes a test signal generator that receives a clock signal including pulses having leading edges and trailing edges that occur at predetermined intervals and selectively generates a modified clock signal by adjusting timing of at least one of the leading and trailing edges of at least one of the pulses. A signal path includes a circuit and receives one of the clock signal and the modified clock signal from the test signal generator.

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