Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2007-09-25
2009-06-02
Luu, Pho M. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189060, C365S230080, C365S230010, C365S230010
Reexamination Certificate
active
07542355
ABSTRACT:
Disclosed herein is a semiconductor storage device including: a memory core having memory cells to be accessed; and an interface circuit having terminals operable to input and output a chip enable signal adapted to select a chip, at least one control signal adapted to control the chip operation, a clock signal adapted to control the chip I/O operation timing and a series of data including a command, address and data; wherein the interface circuit includes at least one input holding unit adapted to hold the control signal, and the interface circuit processes the control signal after loading it temporarily into the first input holding unit.
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Japanese Office Action issued Sep. 16, 2008 for corresponding Japanese Application No. 2006-275096.
Kozakai Kenji
Nakajima Tsutomu
Sakui Koji
Kananen Ronald P.
Luu Pho M.
Rader & Fishman & Grauer, PLLC
Sony Corporation
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