Device and method for JTAG test

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Details

C365S201000, C714S724000, C716S030000, C702S117000

Reexamination Certificate

active

07613968

ABSTRACT:
In order to realize a JTAG test of a printed board including a semiconductor device having JTAG test unsupported input/output terminals inside thereof, one device is logically divided into two devices such as a JTAG test supported device and a JTAG test unsupported device, boundary scan FFs are inserted between the two devices to be combined with another device configured in the same way and the JTAG test unsupported parts of both devices are equivalently combined to be regarded as one JTAG test unsupported device. Then, this device is sandwiched by the JTAG test supported devices and a JTAG test is conducted.

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Kazumi Sakamaki, “JTAG test-Basics and Applications”, Mar. 15, 2003, pp. 53-54, CQ Publishing Company.

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