Cell region layout of semiconductor device and method of...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S907000, C257S908000

Reexamination Certificate

active

07615815

ABSTRACT:
A cell region layout of a semiconductor device formed by adding active regions in the outermost portion of a cell region, and a method of forming a contact pad using the same are provided. The layout and the method include a first active region formed at the outermost portion of the cell region, and having the same shape as that of an inner active region located inwardly from the outermost portion of the cell region, and a third active region formed by adding at least two second active regions having shapes different from that of an inner active region. Further, an insulating layer fills a portion below a bit line passing the third active region. A lifting phenomenon occurring where an active region is not formed can be prevented by adding the active regions at the outermost portion of the cell region, and a bridge phenomenon occurring when bit lines or a bit line contact and a gate line electrically contact can be suppressed by filling a portion below a bit line with an insulating layer.

REFERENCES:
patent: 5783336 (1998-07-01), Aoki et al.
patent: 2000-019709 (2000-01-01), None
patent: 2000-0015029 (2000-03-01), None
patent: 2001-0060441 (2001-07-01), None

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