Metal gates with low charge trapping and enhanced dielectric...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – Insulated gate formation

Reexamination Certificate

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C438S586000, C438S605000, C257SE21621, C257SE21639

Reexamination Certificate

active

07611979

ABSTRACT:
A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.

REFERENCES:
patent: 5565702 (1996-10-01), Tamura et al.
patent: 6506676 (2003-01-01), Park et al.
patent: 6798026 (2004-09-01), Hu et al.
patent: 7023055 (2006-04-01), Ieong et al.
patent: 2001/0039107 (2001-11-01), Suguro
patent: 2002/0050644 (2002-05-01), Matsumoto et al.
patent: 2002/0179975 (2002-12-01), Wakabayashi et al.
patent: 2003/0027393 (2003-02-01), Suguro
patent: 2003/0211713 (2003-11-01), Suguro et al.
patent: 2004/0104439 (2004-06-01), Haukka et al.
patent: 2004/0256700 (2004-12-01), Doris et al.
patent: 2005/0059198 (2005-03-01), Visokay et al.
patent: 2005/0116290 (2005-06-01), de Souza et al.
patent: 2005/0205947 (2005-09-01), Yu et al.
patent: 2005/0282341 (2005-12-01), Park et al.
patent: 2006/0151846 (2006-07-01), Callegari et al.
patent: 2006/0270204 (2006-11-01), Ku et al.
patent: 2007/0023842 (2007-02-01), Jung et al.
Krishnan et al., Charge Trapping Dependence on the Physical Structure of Ultra-thin ALD-HfSiON/TiN Gate Stacks, IIRW Final Report, IEEE, 2005, pp. 89-90.
Kim et al., Hard and Soft-Breakdown Characteristics of Ultra-Thin HfO2 Under Dynamic and Constant Voltage Stress, IEEE, 2002.
Zafar et al., Charge Trapping Related Threshold Voltage Instabilities in High Permittivity Gate Dielectric Stacks, Journal of Applied Physics, Jun. 1, 2003, pp. 9298-9303, vol. 93, No. 11.
Choi et al., Charge Trapping and Detrapping Characteristics in Hafnium Silicate Gate Stack Under Static and Dynamic Stress, IEEE Electron Device Letters, Mar. 2005, pp. 197-199, vol. 26, No. 3.
Wakabayashi, H., et al., “A Novel W/TINX Metal Gate CMOS Technology Using Nitrogen-Concentration-Controlled TINX Film,” International Electron Devices Meeting 1999, IEDM, Technical Digest, Washington D.C., Dec. 5-8, 1999, pp. 253-256.

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